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Altera_Forum
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15 years ago

altlvds bit alignment question

Hi, I have a noob question. I'm using a Cyclone 3 FPGA and use the ALTLVDS megafunction. The lvds link works fine, but I had a technical question of how the megafunction handles frame bit ali...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I guess, the reported sync problem is caused by a loss-of-lock of the receiver PLL. Basically, the PLL must be reset (by pll_areset) after a stable reference clock is supplied respectively supplied again. As far as I see, no automatic reset is provided for the internal option.