Alternatives to NIOS

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I'm getting a bit frustrated with NIOS and I'd like to consider alternative soft-cores.

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I want something with an area size similar to the /e core, but not at the expense of 6 clocks or more per instruction. This is almost ridiculous for RISC. It is, of course, just a consequence of NIOS being designed around a deep pipeline.

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Sounds like a complaint to me.

You are unknowingly complaining about the pipeline.

In order to execute an instruction, you have to

1 - fetch the instruction from memory,

2 - decode the instruction to determine what registers / memory need to be accessed and what operations will be performed on those operands.

3 - Execute the instruction (add, multiply, etc.)

4 - Access the memory (in the case of instructions that load or store from memory)

5 - Write execution or memory stage results back into registers.

So, you can either do all of theses steps sequentially for every instruction or you can pipeline them. By complaining about the execution time of the /e core you are saying that you don't like the fact that all of the above steps have to be performed sequentially. However, you are also saying that you don't like the logic usage of the /s or /f cores which are pipelined and use a cache. A pipeline is required for efficiency (talking about MIPS).

Now in reality, the above steps can be reduced to a 3-stage pipeline by combining stages. This results in an fmax penalty as more combinatorial logic is required in each of the stages.

Your best bet may be the Microblaze which gives you the option of using a 3-stage pipeline. I don't know what the logic usage would be and of course that would be a different forum. And I'm sure the Microblaze forum would have no problem with complaints about the NIOS.

This soft CPU might fit your needs better:

http://www.zylin.com/zpu.htm

298 LUT @ 125 MHz after P&R with 16 bit datapath and 4kBytes BRAM

http://nibz.googlecode.com VHDL, no software yet, still in optimization phase for logic area minimization.

Currently >280 min. LEs on MAX II. (16 bit) (23% of 1270)

Many compile warnings.

Fully parametric from 5 bit to n bit.

17 operations, all single memory access, supports late read.

No interupts at present.

Optimized for stack style programming, direct threaded code.

BSD licence.

5 register model. double word shift left support.

2 stacks, program counter, and 2 working registers.

Supports WISHBONE Classic Timing when RRD_I = '0'.

Supports late reads when RRD_I = '1'.

Support little-endian half width data transfer using HLF_I multiplexer

Secondary DMA port

Interrupt strategy and timing slack options in development

Any comments welcome.

Get dac2.vhd for FREE, phase ultrasonic 1 bit DAC (16 bits in) from the nibz homepage. Does not yet use DMA bus.

Plans for future:

Various I/O

SDK

UFM and Video

Spectral and Wave Table Audio Synthesis

Reason d'etre:

Open Mini PC (OxPx) resource disenfranchisement

I have a suggestion about handling inputs that need quick responses. Try using TriMatrix arrays set up to do logical functions.

The attached sketch shows how a small statemachine merged with the inputs could produce an address input to a second array which then drives the output.

The 2 stage pipeline first stage generates code, then uses code to generate output.

If further processing is required, then use it more for processing, not as a controller, offload the critical timing to arrays.

The second attachment is a start at using arrays for a microprogrammmed computer.

The possibilities for TriMatrix seem endless.

Thanks to all for your time to read this.

http://nibz.googlecode.com just placed up a quartus archive of a 94% of EPM570ZM100C6 MAX IIZ project. The processor should work, is an improvement. has 40 general IO pins and 16 bit RAM (static) memory bus.

No pin placement done yet, a very tight fit.

cheers

jacko

Hi I am just checking in to see if there is still interest in this topic.

I have a new kind of embedded processor that runs this trivial test case in 51 clock cycles.

36 of the cycles are used by iterations of the for loop. 9 iterations at 4 clocks per.

How does this compare to NIOS?

main()

{

//x = 0x00ff; // 15 | 255;

//x = 1;

if(x == 0)

if(x == 0) y = 2 + 3 * 4 - 4;

else y = 5;

else y = 2*3-4;

while(x == 6) // if x == 6

{

x = x - 7;

}

for(x = 0; x < 9; x = x + 1)

{

y = 10;

}

}

A crude but compilable .bdf shows 5 aluts and about 45K ram bits with slack of 8.189.

*******Just realized a lot of nodes were synthesized away so this data is not correct.

Am I on the right track?

http://nibz.nibzx.co.uk

Well, it's been awhile so here is the NiBZ latest.

Sub VGA 256*288 video

16 bit audio through 1 bit DAC

SPI boot and SD SPI

80MHz in max II

2 (16 bit) MIPS per 10MHz

3 to 1 opcode compression with in place execution

Still only 70% of MAX II 1270 with video and audio and SPI

Fully generic word size

16 bit port (8 ins and 8 outs)

http://code.google.com/p/nibz/downloads/detail?name=nibzx7.vhd&can=2&q= (http://code.google.com/p/nibz/downloads/detail?name=nibzx7.vhd&can=2&q=)

A 16 bit generically programmable core (not fully tested) but many issues fixed, @75% of 1270 MAX II and 85MHz in C5.