Honored Contributor
Honored Contributorhttp://nibz.googlecode.com VHDL, no software yet, still in optimization phase for logic area minimization.
Currently >280 min. LEs on MAX II. (16 bit) (23% of 1270) Many compile warnings. Fully parametric from 5 bit to n bit. 17 operations, all single memory access, supports late read. No interupts at present. Optimized for stack style programming, direct threaded code. BSD licence. 5 register model. double word shift left support. 2 stacks, program counter, and 2 working registers. Supports WISHBONE Classic Timing when RRD_I = '0'. Supports late reads when RRD_I = '1'. Support little-endian half width data transfer using HLF_I multiplexer Secondary DMA port Interrupt strategy and timing slack options in development Any comments welcome. Get dac2.vhd for FREE, phase ultrasonic 1 bit DAC (16 bits in) from the nibz homepage. Does not yet use DMA bus. Plans for future: Various I/O SDK UFM and Video Spectral and Wave Table Audio Synthesis Reason d'etre: Open Mini PC (OxPx) resource disenfranchisement
