Maybe the CIC IP remains defective when it doesn't automatically choose sufficient number of internal accumulator bits so that an anomalous output is _not_ produced with hogenauer pruning option and for the single most negative two's complement input value, as detected when performing a DC linearity test.
Perhaps the customer shouldn't need to add an additional (duplicated) sign bit to the CIC input to fix Altera/Intel CIC internal implementation issues?
Alternatively, if avoiding such problems by adding an additional (duplicated) input sign bit, is seen as a user implementation choice, resource consumption trade-off, by Altera/Intel then at a minimum perhaps the single anomalous output situation should be documented in the Altera/Inte CIC manual suggesting also the possibility of adding an additional (duplicated) sign bit to the input as a workaround, from my humble perspective.
Thanks for your interest and best regards,
JHill1
Occasional Contributor
