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SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Altera Triple Speed Ethernet with DP83848 ethernet board on a Cyclone V GX starter kit

Hello Intel Forums,

I have a Cyclone V GX starter kit (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830). This kit has no ethernet port, so I've added a DP83848 ethernet board (https://www.waveshare.com/dp83848-ethernet-board.htm) by connecting it to the GPIO pins.

I have set up the TSE MAC to run in MII mode, and since the DP83848 board runs in RMII mode, I am using a converter I found here on the intel forums (https://forums.intel.com/s/question/0D50P00003yyMhhSAE/does-the-triple-speed-ethernet-ip-core-support-rmii)

As far as I know, I have the pin connections all set up correctly, as well as the interface between the TSE and the RMII to MII converter.

I've attached my top module to this question. I was unable to attach the qsys system, so here's a link to it: https://particle.phys.uvic.ca/~srdejong/qsys/Nios_CPU_qsys.qsys

I set up a nios II project using the Simple Socket Server template. I can compile the software and load it onto the board, but when I do, the ethernet PHY is not detected:

InterNiche Portable TCP/IP, v3.1 
 
 
Copyright 1996-2008 by InterNiche Technologies. All rights reserved. 
 
prep_tse_mac 0
 
 
Can't read the MAC address from your board. We will assign you
 
a MAC address.
 
 
Your Ethernet MAC address is 00:07:ed:ff:00:17
 
prepped 1 interface, initializing...
 
[tse_mac_init]
 
INFO   : TSE MAC 0 found at address 0x000c3000
 
ERROR  : MAC Group[0] - No PHY connected!
 
ERROR  : PHY[0.0] - No PHY connected! Speed = 100, Duplex = Full
 
TSEMAC SW reset bit never cleared!
 
OK, x=10002, CMD_CONFIG=0x00002000
 
 
MAC post-initialization: CMD_CONFIG=0x04000200
 
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
 
mctest init called
 
IP address of et1 : 0.0.0.0
 
Created "Inet main" task (Prio: 2)
 
Created "clock tick" task (Prio: 3)

I'm not sure what's going on or how to debug this. I've connected a signaltap instance to various signals. I get activity on the MDC bits and the TX and RX clocks, but the MDIO signals remain at 0.

Any assistance you could provide would be very much appreciated.

Thanks,

-Sam

4 Replies

  • SDe_J's avatar
    SDe_J
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    I have switched to a different RMII to MII interface, as in the attached qar file. I'm getting a new error now when I run the simple socket server example:

    InterNiche Portable TCP/IP, v3.1 
 
Copyright 1996-2008 by InterNiche Technologies. All rights reserved. 
prep_tse_mac 0
 
Can't read the MAC address from your board. We will assign you
a MAC address.
 
Your Ethernet MAC address is 00:07:ed:ff:00:17
prepped 1 interface, initializing...
[tse_mac_init]
INFO    : TSE MAC 0 found at address 0x000c3000
WARNING : Unknown PHY found at PHY address 0x00 of MAC Group[0]
WARNING : Please add PHY information to PHY profile
INFO    : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO    : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO    : PHY[0.0] - Auto-Negotiation PASSED
WARNING : Unknown PHY found at PHY address 0x01 of MAC Group[0]
WARNING : Please add PHY information to PHY profile
WARNING : PHY[0.X] - Mapping of PHY to MAC failed! Make sure the PHY address is defined correctly in tse_mac_device[] structure, and number of PHYs connected is equivalent to number of channel
 
...... contiues for PHY addresses 0x02 to 0x1e....
 
WARNING : Unknown PHY found at PHY address 0x1f of MAC Group[0]
WARNING : Please add PHY information to PHY profile
WARNING : PHY[0.X] - Mapping of PHY to MAC failed! Make sure the PHY address is defined correctly in tse_mac_device[] structure, and number of PHYs connected is equivalent to number of channel
WARNING : MAC Group[0] - Number of PHY connected is not equal to the number of channel, Number of PHY : 32, Channel : 1
INFO    : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO    : PHY[0.0] - Auto-Negotiation PASSED
INFO    : PHY[0.0] - Checking link...
INFO    : PHY[0.0] - Link established
WARNING : PHY[0.0] - PHY not found in PHY profile
INFO    : PHY[0.0] - Speed = 100, Duplex = Full
OK, x=0, CMD_CONFIG=0x01000000
 
MAC post-initialization: CMD_CONFIG=0x05000203
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
mctest init called
IP address of et1 : 0.0.0.0
Created "clock tick" task (Prio: 3)

    I am using Quartus 16.1 and the eclipse nios version associated with it. The simple socket server is identical to the template in eclipse nios.

    Thanks for any help,

    -Sam

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
    Icon for Contributor rankContributor
    7 years ago
    Hie, The Triple Speed Ethernet does not support RMII. As you are aware it only support RGMII, MII and others. The converter card is not Intel's recommended method as we have not validated it in-house. Hence, this is out of specs use case. Hence, I cannot guarantee this will work. However, I will try to guide you by providing some guidelines on the next debug steps. It seems you have done the first level due diligence by checking if the Physical connections and Phy clocks can be detected and it seems to be detected. What I recommend next is; you could try to access each Phy device by writing the Phy address to the MDIO registers. Ensure the AVMM is accessing the MDIO registers correctly. Please refer to section 4.1.12 and subsequent sections of user guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf Regards, Nathan
    • SDe_J's avatar
      SDe_J
      Icon for Occasional Contributor rankOccasional Contributor
      7 years ago

      Hi Nathan,

      Thanks for your advice, I'll look into this.

      Just to be clear, I'm not using a physical coverter to convert the MII from the triple speed ethernet into RMII, I'm using a VHDL module. I only have one PHY attached, so I'm confused that the simple socket server thinks there's multiple.

      -Sam

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
    Icon for Contributor rankContributor
    7 years ago
    Hie Sam, Ok, I have a better understanding on how the MII to RMII conversion is done. Please try my suggesting above to check if MDIO is accessing AVMM registers properly. Regards, Nathan