Honored ContributorHi, i'm going to use lvds pairs on max 10m80e board.
There is Altera Soft Lvds IP in Q14.1 Can i use the ip core for transmitting data throught lvds pairs? I use camera link base protocol (7 is ser factor). Speed i need is about 20Mbps. How i can simulate the ip core? Just like an any ip core? I've tried but the core doesnt response
Honored ContributorThere should not be any issues with that.
Perhaps you might want to put more description to your failure symptoms.Honored ContributorWouldnt 20Mbps would be a little too low for J = 7.
If not mistaken the minimum you would need 70Mbps for J =7.Honored ContributorIf the supported minimum data rate is higher than your requirement, you may try to look into performing oversampling at your receiver side to step down the data rate.
Honored ContributorI've created project.
https://www.alteraforum.com/forum/attachment.php?attachmentid=10918 I'm using external pll, counter and altera soft lvds. serialization factor is 4. So the core should take 4 data bits from counter and serialize to 1 bit. I'm checking by signalTab. The core doesn't work. I took pll settings from max 10 lvds UG. (400 for inclock and 80 MHz for syncclock) What could be wrong?Honored ContributorFabian the transmitter model doesn't work at all.
I tryed most simple model with internal PLL. I can see that the internal PLL is locked but nothig comes out. The receiver works fine. CésarHonored ContributorHi Fabian,
Probably you could try simulating your design in Modelsim to see if similar issue observed?
