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Altera_Forum
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17 years ago

Altera FFT Vs Matlab FFT. Strange Results

Hi, I’m testing some FFT Altera Core using those parameters: 1)Single Streaming or Burst 16K length FFT 2)12-14-16 bits input REAL data (pseudorandom code {-1,1}) 3)same bits for twiddle...
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Altera_Forum
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16 years ago

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Hi,

It seems that I am having the same issue.

My fft_sink_ready signal (called out_sink_ready) is being set to 0 after being asserted to 1 a couple of cycles before. I do not know why this is happening. Any help with this matter will be greatly appreciated.

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I had this problem, too. Go to the wizard you created the IP-core with. Check the checkbox including the global clock enable signal. Apply a logical high level signal to the input. Then the IP-core should not stop working after the first cycles.