Forum Discussion
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- Hi, I faced that problem before. But for me, I was able to see outputs after i decrease my clock period from 10ns to 1ns. Maybe you could try that. --- Quote End --- 1ns clk period means 1000MHz(1GH). Too good to be true for any fpga. I am afraid you are on the wrong path.