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Altera_Forum's avatar
Altera_Forum
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17 years ago

Altera Ethernet MAC - TX Overflow at ST interface

Hi,

I am using the 10/100/1000Mbps TSE from Altera and have some problems when I provide a burst of data to the TSE through the Avalon ST interface.

What I see is this:

The packets are provided to the TSE core with Start of Packet and End of Packet handshake. I forced the core to 100Mbps, but the Avalon ST is working on 50MHz / 32 bit.

After 5 complete packets the TSE deasserts its ready signal half way packet 6, this is allowed of course, but it never deasserts its ready signal when it has transmitted all data from its fifo. Of course in which packet it will deassert its ready is determined by the fifo settings, but the issue is: why does it not assert its ready after the fifio is transmitted? Are there knwon issues reagrding this IP and this case?

Thanks in advance!

Bert

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I'm using this core without any issues.

    I can't think of why it would never reassert its ready signal for the 6th packet after transmitting 5 packets successfully. The only thing I can think of is that you are disabling the transmitter in the command config register (bit 0) for some reason.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi,

    I discovered a problem with the tx_almost_full setting of the TSE.

    This value is related to the Ready Latency of the Avlon Streaming Interface, which is set to 0. According to the user guide the tx_almost_full must be set to 3.

    I was not aware of this requirement and still can not udnerstand why the threshold is linked to the Ready Latency. In the design the tx_almost_full was set to 8 and I though the TSE should deassert its READY when there are at most 8 words of free space ...

    When I set the tx_almost_full to 3, which matches with the READ Latency of 0 everything work according my expectation. So, the final question is, why is the tx_almost_full setting linked to the READY Latency ?

    Bye,

    Bert