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evyatar's avatar
evyatar
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10 months ago

altera_eth_1588_tod IP

Hi,

I am experiencing an issue with the altera_eth_1588_tod IP (for Arria 10 - 10AX115S2F45I1SG) when providing it with a 156.25 MHz clock.

To test its accuracy, I implemented a counter and counted 156,250,000 / 2 clock ticks. I then triggered Signal Tap to observe the TOD integer values. However, instead of the expected 0.5-second duration, I noticed a deviation of approximately 480 ns.

The IP is taken from the example design, and I have not modified its configuration. It appears to be correctly set up, but I may be missing something—I'd appreciate your guidance.

To verify, I performed the same test using the altera_eth_1588_tod IP configured for a 125 MHz clock, and in that case, the results were precise.

Are you aware of any known issues with this IP when operating at 156.25 MHz?

I have attached my IP configuration for your reference.

Looking forward to your insights.

Best regards,

Evyatar.

4 Replies

  • evyatar's avatar
    evyatar
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    please note that I added a little modification to the attached qsys file, since without this change I couldn't upload the file.

  • Hi Evyatar,


    Good day to you.

    May I know which quartus version you're working with?

    I do find a known issue on TOD latency. Kindly let me know if it helps.

    But the issue have been resolved Quartus version 18.0 onwards. If you're using the latest version, this shouldn't be related.


    Kindly let me know if it answer your query else I'll debug further on this.


    Regards,

    Pavee


    • evyatar's avatar
      evyatar
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      Hi Pavee,

      I'm using quartus prime version 21.0 build 842 10.21.2021 sj standard edition

      thanks for your help

  • Hello,


    The clock for ARRIA 10GX SI Development Board is meant 125MHz. So what you're observing while feeding 156MHz is expected.

    Kindly refer to Installer Package (Production Edition) › and look for devkit schematic and check the clock conf.


    It is expected observation as you're supplying wrong clock source. The design works fine with 125MHz and you've confirmed it as well. Hence, I shall go ahead and close the case.


    I now transition this thread to community support.

    If you have a new question, feel free to open a new thread to get the support from Altera experts.

    Otherwise, the community users will continue to help you on this thread.


    Regards,

    Pavee