Forum Discussion

New Contributor

10 months ago

altera_eth_1588_tod IP

Hi, I am experiencing an issue with the altera_eth_1588_tod IP (for Arria 10 - 10AX115S2F45I1SG) when providing it with a 156.25 MHz clock. To test its accuracy, I implemented a counter and counted...

altera_eth_1588_tod_10g.qip.txt8 KB

altera_eth_1588_tod_10g.qsys.txt5 KB

Ethernet

evyatar

New Contributor

10 months ago

please note that I added a little modification to the attached qsys file, since without this change I couldn't upload the file.

Forum Discussion

altera_eth_1588_tod IP

Recent Discussions

About Design Limitations and Known Issues

About Dual Simplex for Agilex 3

Where is High Speed Transceiver Demo Design in FPGA Wiki ?

Can't find Agilex 7 M I/O PLL Reconfiguration Design Example

Enabling DFE Adaptation on Cyclone 10 GX