Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Altera Dual Port RAM

Hi Guys, I've written a program in VHDL to access CIS and get data and transfer the data over USB using cypress USB transceiver CY7C68013A. CIS : 1728 Pixels/Line, Output in three parts of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

your problem needs simulation to find out where data is shifted. It is several stages and I wouldn't suspect the ram to do that.