altera_dma driver for PCIe

The low throughput numbers that everyone is seeing in DMA module is due to DMA timeout happening.

DMA timeout is occurring because the Descriptor controller FIFO addresses for Read and Write in altera_dma.h do not

match the values in FPGA (reported in QSYS).

The base addresses of wr_dts_slave and rd_dts_slave in QSYS and the defines WR_CTRL_BUF_BASE_* and RD_CTRL_BUF_BASE_* in altera_dma.h should match.

So basically if your addresses in FPGA are:

rd_dts_slave - 0x1_0000 (Base)

wr_dts_slave - 0x1_2000 (Base)

Then altera_dma.h should define:# define RD_CTRL_BUF_BASE_LOW 0x00010000# define RD_CTRL_BUF_BASE_HI 0x00000000# define WR_CTRL_BUF_BASE_LOW 0x00012000# define WR_CTRL_BUF_BASE_HI 0x00000000