Altera Clock Control Block select signal

I was planning on switching it relatively rarely, but the downstream logic would running and not be in reset. The module has a "glitch free" option that would have been enabled.

However, It ended up including this module made the fitter unhappy (the Fitter produced an error message saying it couldn't fit in PLL2, with no explanation why) so I reverted back to the previous implementation, a simple register based clock divider. It works and met the Recommended Clock-Generation Technique diagram as shown in Figure 5-4 in http://www.altera.com/literature/hb/qts/qts_qii51006.pdf