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dicas3d's avatar
dicas3d
Icon for New Contributor rankNew Contributor
3 years ago
Solved

altera_avalon_new_sdram_controller

I have a project with Dev board max1000 and altera_avalon_new_sdram_controller and in the last version of quartus prime lite give an error that I can't found this module in Qsys. Today I'm writing to ...
Cxl
Memory
  • dicas3d's avatar
    dicas3d
    3 years ago

    I picked an Verilog Model from manufacturer. This is the only thing that is provided as IP Core from him. This is a file .vp and .v for 

    NC-Verilog

    And I don't know how use as an Qsys component. The main file is the .vp.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello!


For your information, the SDRAM Controller IP is already End Of Life.

If you want to use the IP, you might consider to use older Quartus version such 18.1 and earlier.


Besides, this design was created in Quartus Prime version 17.0.

For better functionality, you need to run it in Quartus version 17.0 as well.


Regards,

Adzim



dicas3d's avatar
dicas3d
Icon for New Contributor rankNew Contributor
3 years ago

Info (125068): Revision "NIOSDuino" was previously opened in Quartus Prime software version 18.1.0 Lite Edition. Created Quartus Prime Default Settings File C:/Users/Utilizador/Downloads/nios_duino-master/nios_duino-master/contrib/max1000/NIOSDuino_restored/NIOSDuino_assignment_defaults.qdf, which contains the default assignment setting information from Quartus Prime software version 18.1.0 Lite Edition.

And in the link here is the screenshot of qsys