altera 13.0 uniphy pin assign script fails if adv_netlist_opt_synth_gate_retime is on

FWIW, the altera 13.0 ddr2 uniphy pin assign script (against stratix III) appears to fail if "adv_netlist_opt_synth_gate_retime" option is on. The workaround is to turn the "adv_netlist_opt_synth_gate_retime" option off.

This issue is service request 10962459 at Altera.

I see some error messages like this from the pin assignment script.

Warning (332174): Ignored filter at timedDataSys_mem_if_ddr2_emif_p0_pin_map.tcl(496): timedDataSysInstance|mem_if_ddr2_emif|s0|sequencer_scc_mgr_inst|scc_upd[0] could not be matched with a keeper

Warning: timedDataSys_mem_if_ddr2_emif_p0_pin_map.tcl: Could not find any Config CK pins

Critical Warning: timedDataSys_mem_if_ddr2_emif_p0_pin_map.tcl: Failed to find PLL clock for pins timedDataSysInstance|mem_if_ddr2_emif|s0|sequencer_scc_mgr_inst|scc_upd[0]

Warning (332174): Ignored filter at timedDataSys_mem_if_ddr2_emif_p0_pin_map.tcl(484): _UNDEFINED_PIN_ could not be matched with a node or keeper or port or register or pin or net or combinational node

Error (23031): Evaluation of Tcl script ./submodules/timedDataSys_mem_if_ddr2_emif_p0_pin_assignments.tcl unsuccessful

Error: Quartus II 64-Bit TimeQuest Timing Analyzer was unsuccessful. 1 error, 4 warnings

Error: Peak virtual memory: 944 megabytes

Error: Processing ended: Wed Jun 12 00:08:13 2013

Error: Elapsed time: 00:00:10

Error: Total CPU time (on all processors): 00:00:09

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ERROR: Argument <node_object> is an object filter that matches no objects. Specify one matches only one object.

while executing

"get_node_info -name $clock_id"

(procedure "timedDataSys_mem_if_ddr2_emif_p0_get_pll_clock_name_for_acf" line 2)

invoked from within

"timedDataSys_mem_if_ddr2_emif_p0_get_pll_clock_name_for_acf $pins(pll_config_clock) "pll_config_clk" "

("foreach" body line 108)

invoked from within

"foreach inst $instances {

if { [ info exists pins ] } {

# Clean-up(continued in attached text file)