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Altera_Forum
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11 years ago

Altddio - rgmii

Hi, I'm preparing design on Cyclone V with RGMII connection. I read AN 477 ("Designing RGMII Interfaces with FPGAs and HardCopy ASICs") about it and I understand what is necessary to do. I miss on...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

OK, I can connect RX and TX data on DQ pins but how about RX_CLK and TX_CLK? Has they be connected on dedicated CLK pin or on the DQS pin? I can imagine, that the receive clock is on DQS pin and transmit clock is on dedicated CLK pin, but I'm not sure that it is right solution.