ALTASMI_PARALLEL in full synchro design. Can I use the same clock and edge (rising edge ) for clkin and the rest of the design?

Thank you for your answer. When you said same clock source, that imply the same front edge, that right? It's not clear for me when I check the Active Serial Memory Interface (ALTASMI_PARALLEL) Megafunction User Guide (UG-ALT1005-4.2) . For example for a Write : [cid:image001.jpg@01D4A8D6.E2E938F0] [cid:image002.jpg@01D4A8D6.E2E938F0] What is the best solution to manage inputs signals (write , wren, shift_bytes, data_in.....) and to respect the propose timing? 1/ using clk positive edge for signals generation and clk negative edge for ALTASMI_PARALLEL clkin with constraints on Clk Frequency. Or 2/ using same clock positive edge for both with appropriate timing constraints on ALTASMI_PARALLEL. In this case, can-you help me to define the appropriate constraints for the IP? Same question for the ALTEREMOTE_UPDATE IP. Thank you for your help. Regards, Nathalie Schlumberger-Private