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New MemberAgilex5 transceiver in 64/66b mode
Hi, I'm working on a design to implement a high speed bidirectional interface using POC. To achieve highest throughput we should use 64/66 scrambling (which Agilex5 XCVR supports). It doesn't seem clear to me how to config the data bus and what option to select to run the XCVR in that mode.
when I select PCS66, I need to provide scrambled data (i.e. build my 64/66 scambler myself).
Selecting IEEE_MII port mapping is an Ethernet interface - which I don't want. So that's no option.
Selecting FLEXE_66 - well, again 66-bit bus meaning I need to scramble the data myself.
Can somebody explain how to get the internal scrambler to operate and how to map 64bit data from logic to the Tx_Parallel(79:0) bus?
What am I missing?
1 Reply
CheepinC_alteraRegular Contributor
Yes, you are right, the GTS internal scrambler is present in FlexE mode but not in PCS66 mode.
Regarding the Tx_Parallel[79:0] bus mapping for PCS Direct (IEEE_FLEXE_66 / PCS66):
For PCS modes IEEE_FLEXE_66 and PCS66, the PMA interface width is 32 bits (DW), with elastic FIFOs on both the PMA interface (TX/RX) and phase compensation FIFOs on the core interface. GTS Transceiver PHY User Guide
The 80-bit parallel data bus carries the 66-bit block in specific bit positions. The i_tx_valid / i_tx_pcs66_valid signal must be driven high to qualify the 66-bit data block on the i_txd / i_tx_pcs66[65:0] input data bus. GTS Transceiver PHY User Guide The two LSBs of the 66-bit word are the sync header bits: drive the i_txd[65:0] / i_tx_pcs66[65:0] bus with the 66-bit data blocks from the source, where the two least significant bits are the header sync bits. GTS Transceiver PHY User Guide
In summary, your data mapping flow for IEEE_FLEXE_66 is:
Present your raw (unscrambled) 64-bit payload + 2-bit sync header as a 66-bit block on i_txd[65:0].
Assert i_tx_valid to qualify the block.
The hard PCS scrambles it internally before serialization.
