Agilex5 transceiver in 64/66b mode

Yes, you are right, the GTS internal scrambler is present in FlexE mode but not in PCS66 mode.

Regarding the Tx_Parallel[79:0] bus mapping for PCS Direct (IEEE_FLEXE_66 / PCS66):

For PCS modes IEEE_FLEXE_66 and PCS66, the PMA interface width is 32 bits (DW), with elastic FIFOs on both the PMA interface (TX/RX) and phase compensation FIFOs on the core interface. GTS Transceiver PHY User Guide

The 80-bit parallel data bus carries the 66-bit block in specific bit positions. The i_tx_valid / i_tx_pcs66_valid signal must be driven high to qualify the 66-bit data block on the i_txd / i_tx_pcs66[65:0] input data bus. GTS Transceiver PHY User Guide The two LSBs of the 66-bit word are the sync header bits: drive the i_txd[65:0] / i_tx_pcs66[65:0] bus with the 66-bit data blocks from the source, where the two least significant bits are the header sync bits. GTS Transceiver PHY User Guide

In summary, your data mapping flow for IEEE_FLEXE_66 is:

Present your raw (unscrambled) 64-bit payload + 2-bit sync header as a 66-bit block on i_txd[65:0].

Assert i_tx_valid to qualify the block.

The hard PCS scrambles it internally before serialization.