Forum Discussion
New ContributorAgilex5 o_tx_ready and o_rx_ready not asserting
Frequent ContributorBecause both TX and RX ready remain low, I would first suspect a shared clock/reset prerequisite—i_system_pll_lock, i_refclk_ready, o_pll_lock, or missing/incorrect core clocks—rather than the IEEE_FLEXE_66 payload interface.
Probe these signaltap (with power up trigger). Set to Transitional.
i_refclk_ready
o_pll_lock
i_system_pll_lock
i_tx_coreclkin
o_tx_clkout (you cannot tap on clk signals. Instead use it to drive some counters, then tap on the counter to check for toggling activity)
o_tx_pll_locked
o_tx_reset_ack
i_tx_reset
i_src_rs_req
o_src_rs_grant
i_src_rs_grant
o_tx_ready
New Contributorapparently the clocks are running (TxCount_r and RxCount_r are counters in these respective clock domains).
nInit_Done is refClk_ready (PLL input), PLL_lock, rst_req and rst_grant are handshaking, TxReset_Ack and RxReset_Ack are behaving as expected, but as you can see ... Ready remains dead.
I noticed during setting up signaltap that the signals are all in the int_osc clock domain. And my LaneSequencer (the bring up sequence for GTS Tx and Rx) is in a 100MHz SysClk domain.
What do you mean with 'incorrect core clock'? There was an errata on version 25.3, but neither 25.3.1 nor 26.1.0 seem to be affected by this erratum?
