Occasional Contributor
Occasional ContributorAs I undrestand settings for MSI interrupt and MSI-X interrupts are not shared. So i'm not sure if we can refer to that setting for MSI-X.
In our design we use only PCIe core and some additional components like AXI briges and DDR controller. But the core logic is our own. But the PCIe subsustem was taken from generated example design unchanged.
We run into the same issue with MCDMA for PCIe with Avalon buses. So it seems there is the same cause.
I just want to find out if we can take a look at some interface, so probably we will be able to see if write TLP for incoming MSI-X request is actually being sent, so we could localize the problem.
