Occasional Contributor
Occasional ContributorAt the moment we cant find anything wrong according to your list. Is there any way to make sure that
Also one more question. As I understood from the doc MSI-X messages are written by MCDMA, but should we enable it or initialize if in our case we don't use it at all?
Regular ContributorHi Mikhail_a ,
As I understood from the doc MSI-X messages are written by MCDMA, but should we enable it or initialize if in our case we don't use it at all?
>> If I refer to the user guide , the default value is 1. If you dont use it at all perhaps you can set it as zero
our pcie endpoint actually sends MSI-X TLP to the root complex?
the acual write transaction from the root complex was issued in the host system?
>> Based on my understanding on PCIe architecture , the Endpoint generates MSI-X by sending a Memory Write TLP upstream. The Root Complex does not issue that write; it receives it and converts it into a CPU interrupt.
What is the design you are using ? is it custom design ?
Or design generate purely from our IP catalog ?
If this is custom design, I would suggest to generate one from our IP catalog
https://docs.altera.com/r/docs/847470/25.1.1/gts-axi-multichannel-dma-ip-for-pci-express-user-guide/bam-bas-mcdma-mode
Regards,
Wincent
