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ArtfulWombat's avatar
ArtfulWombat
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2 years ago

Agilex 7 M EMIF Mode Register Access

I'm interested in performing Mode Register Reads (MRR) and Mode Register Writes (MRW) when using the Agilex 7 M EMIF with DDR5 memory connected to the FPGA (not HPS). I looked through the command mailbox interface for the EMIF Sequencer in section 3.2 of UG 772538 version 2024.07.08, but did not see any commands for mode register access. Is there another interface I missed or maybe additional mailbox commands for this purpose?

6 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor

    Hello ArtfulWombat,


    I think the Agilex 7 M series EMIF IP doesn't has that feature access.


    Regards,

    Adzim




    • ArtfulWombat's avatar
      ArtfulWombat
      Icon for New Contributor rankNew Contributor

      Hi Adzim,

      Do you know if there is a way to gain access to that feature? It is important for our application to be able to read and write the mode registers.

    • ArtfulWombat's avatar
      ArtfulWombat
      Icon for New Contributor rankNew Contributor

      Hi Adzim,

      Do you think you could put me in contact with someone who might have more information on this feature?

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor

    Hi @ArtfulWombat ,

    Since there is no further question from your end, I will transfer this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts.

    Otherwise, the community users will continue to help you on this thread.

    Thank you.