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colm's avatar
colm
Icon for New Contributor rankNew Contributor
1 year ago

Agilex 7 I-series EMIF toolkit conflicting results

Hello, We have a custom board with AGIB022R31B2E1V implementing 4 identical EMIF interfaces. When tested with the EMIF toolkit for re-calibration and margining, we got conflicting results. First,...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,


Thank you for submitting your question in Intel Community.

I'm Adzim, application engineer will assist you in this forum.


From my point of view, I think your board is healthy based on the result of the calibration and traffic generator status.

You should be worried if there are some issue with calibration report or data corrupting during write or read transaction.


I think the read margin is not 468ps but I need to double check on how to calculate the margin from the EMIF Debug Toolkit.


Do you have any other doubt with EMIF Debug Toolkit?


Regards,

Adzim


colm's avatar
colm
Icon for New Contributor rankNew Contributor
1 year ago

Hi Adzim,

Thank you for your reply. We do have another design/board using the exact same FPGA and EMIF interfaces, but have the correct responses. Please see snapshots below:

Back to the original bad calibration reports, I believe the -234ps to 234ps is the preset values, and I guess something caused the calibration finished pre-maturely and the margins were not updated.

This issue is also filed in https://premiersupport.intel.com/IPS/s/case-detail?recordId=500Ho00001MjUOkIAN&isCase=true

but no owner has been assigned yet. Please see if you can push someone to look into it.

Regards,

Colman