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frankbarone's avatar
frankbarone
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8 months ago

Agilex 7 emif ip questions

Hello,

I downloaded this document from your site, ug-ag-emi-683216-780962.pdf. All my questions refer to this document.

In here, on page 78, there is no information about the width of the address bus. Upon searching entire document, I saw that on page 315, it is mentioned that address bus is 31 bits wide.

But the example design has it as 29 bits wide.

What is the width of address bus on the emif ip for agilex 7 ? Is it 29 or 31?

Is there any documentation about address mapping between agilex 7 emif ip and a ddr4 dimm?

Is there any documentation which has waveforms and other details about reading and writing to this emif ip. I did not see such diagrams in this document.

Your user guide has lot of room for improvement. Though there is lot of information, I could not find basic details about using the ip.

Is there a better document than the one I am using?

Thank you,

Frank

Memory

4 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    8 months ago

    The address bus width of the Avalon interface is as wide as needed to access the controller. Page 323-324 of the document you mention (I had to find the document you mention; including links to documents helps in a forum) shows an example of address mapping but it depends on the Address Ordering parameter set when you parameterize the IP.

    The interface is standard Avalon so you should just use the Avalon spec: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/introduction-to-the-interface-specifications.html

    • frankbarone's avatar
      frankbarone
      Icon for New Contributor rankNew Contributor
      8 months ago
      Thank you.
      I will give you link to the document in future.

      Please explain What you mean by “address bus is as long as controller needs” ?
      Isn’t the width of the address bus a constant value for the emif controller ?
      If not, what does the width of the address bus depend on? Is there an example anywhere?
      I am to use emif controller. It did not occur to me to use Avalon user guide. Mentioning it in the user guid would help.
      Could also answer my other question about read write request. I am asking again here -
      Is there any example of sending read and write request to the memory controller and waveforms for the same? Though it is Avalon interface, how read and write request are sent depends on how memory controller handles them.
      Thank you,
      Frank
      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        8 months ago

        No, the address bus width may be different depending on the memory capacity and options chosen for the controller as mentioned. I pointed you to one example of what the address bus might look like (pages 323-324).

        Avalon is a known standard with Altera IP so I guess the user guide is assuming you know what it is. Surprisingly, you're right, there is no link to the spec in the EMIF IP user guide.

        The best way to understand how to issue commands to the controller IP is to generate the EMIF example design. You can take the example design and use it as a starting point for your own and then just replace the traffic generator with your own design once you see how it works issuing requests to the IP.

  • Zehui's avatar
    Zehui
    Icon for New Contributor rankNew Contributor
    8 months ago

    Hello Frank,

    The width of amm_address is heavily dependent on the external memory. Let's use an example to understand it:

    Assuming I have a single rank DDR4 interface constructed using 16Gb x8 components, we can get the following information by referring to the DDR4 datasheet.

    CS width = 1 (single rank)
    Chip ID width = 0 (non-3DS device)
    Bank Group width = 2 (from datasheet)
    Bank Address width = 2 (from datasheet)
    Row width = 17 (from datasheet)
    Column width = 10 (from datasheet)

    When we select the "CS-CID-Row-Bank-Col-BG" scheme in EMIF IP, the definition of amm_address would be:

    amm_address[27:11] = Row[16:0]
    amm_address[10:9] = Bank[1:0]
    amm_address[8:2] = Column[9:3] (The lower 3 bits are omitted because DDR4 uses a 8n prefetch architecture)
    amm_address[1:0] = BG[1:0]

    The field "CS" is discarded because there is only one rank. There is no "CID" either as this is a non-3DS scenario.


    Since the EMIF IP uses standard Avalon Memory Mapped interface, you may refer to the Avalon specification for the usage and waveforms.
    Additionally, simulating an EMIF example design and viewing its waveform is also a good starting point.

    Here are the timing diagrams in case you would need them now:

    Thanks.