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I found the kit CD-ROM in the folder you pointed out: devkit/Stratix_DSP_Pro-v1.3.0_CD.zip
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Great.
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The schematics PDF is available after installing this kit. Now I need to figure out how to create an universal constraint file with all FPGA pinout.
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Here's what I do. Look for a design example in the kit, one that uses all or most of the pins on the FPGA. Open the .qsf file for the project, and you should see the pin assignments as 'set_location_assignment' lines.
Copy all those lines to a new file. Use an editor and keep only the pin name and the pin number.
Look at the attached file (rename it pinout.tcl). You'll see that this file contains Tcl commands to create a Tcl variable called 'pin'. The variable is actually a Tcl array, with the pin names as every element in the array. The 'value' of each element is the pin number. Down the bottom of this file, there is a Tcl loop that converts the Tcl array into Quartus pin assignments. I personally find this easier to maintain, but you could just as easily have 'set_location_assignment' commands on every line.
You can source this Tcl file from Quartus and it will setup the pin assignments for every design that uses this board. The caveat is that your top-level VHDL or Verilog entity should have all the same signals defined, otherwise you get warnings about invalid pin assignments.
Once you have the first version of your pinout file, go through the schematic and make sure every pin is correct, and that all pins used have an assignment.
Have fun!
Cheers,
Dave
Honored Contributor
