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Altera_Forum
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17 years ago

Adding SDRAM meeses with LVDS communication

Hi, I have a design comprising PCIe, DDR2, and multiple LVDS channels to connect a Stratix II GX FPGA to a Cyclone III FPGA. Using Signaltap I have verified that my design works well when I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Just one important warning before you commit further. It happened to me once. Don't depend 100% on signaltap. I used to get wrong data from signaltap in some builds and we termed it clock slip. The best check is in firmware itself, device a simple internal test to latch any error and flag it out on led.