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Honored Contributor
Honored ContributorAdding SDRAM meeses with LVDS communication
Hi, I have a design comprising PCIe, DDR2, and multiple LVDS channels to connect a Stratix II GX FPGA to a Cyclone III FPGA. Using Signaltap I have verified that my design works well when I ...
Altera_ForumHonored Contributor
Honored ContributorThe fact, that the LVDS connection is inter-board suggests, that Rysc's assumption of signal quality issues may be correct. In this cases, you should check the LVDS waveforms and possible changes when operating the RAM.
Did you try to adjust the LVDS receiver phase in both cases? Is the word alignment guaranteed by the reference clock unequivocally?
