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Honored Contributor
Honored ContributorAdding SDRAM meeses with LVDS communication
Hi, I have a design comprising PCIe, DDR2, and multiple LVDS channels to connect a Stratix II GX FPGA to a Cyclone III FPGA. Using Signaltap I have verified that my design works well when I ...
Altera_ForumHonored Contributor
Honored ContributorFvM,
I am using a PLL on stratix to generate two clock signals - one to drive SERDES Tx on Stratix and another to drive a PLL on Cyclone. Cyclone PLL in turn generates the clock for SERDES Rx. The error is that when I use SignalTap to view 10-bit data received at Cyclone it does not match the 10-bit data sent by the Stratix. Rysc, DDR2 is on the SIIGX. When I leave its constraints in the project but remove the module from my design, things work fine. Did you mean that I should keep it in design but may be leave it unconnected or disable the clocks driving it? I have one lane going from Stratix to Cyclone, which is corrupted, and 4 lanes coming back from Cyclone to Stratix, which seem correct. (I am going to re-verify that since I did that test 2 days back). The stratix board is the development kit while Cyclone board is a custom one. Thanks you guys for such prompt responses.
