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Altera_Forum
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17 years ago

Adding SDRAM meeses with LVDS communication

Hi, I have a design comprising PCIe, DDR2, and multiple LVDS channels to connect a Stratix II GX FPGA to a Cyclone III FPGA. Using Signaltap I have verified that my design works well when I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Is the DDR2 on the SIIGX or Cyclone III? Can you add something to disable the DDR2 in system, so it's the same place and route you can see it work and then not work? Have you verified it it's a single lane of multiple lanes that are corrupted, or even the whole thing?

My guess is there's some sort of board-level issue. Ground-bounce, cross-talk, SSN, etc., but it's hard to say. Good luck.