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Altera_Forum
Honored Contributor
Honored ContributorAdding SDRAM meeses with LVDS communication
Hi, I have a design comprising PCIe, DDR2, and multiple LVDS channels to connect a Stratix II GX FPGA to a Cyclone III FPGA. Using Signaltap I have verified that my design works well when I ...
Altera_ForumHonored Contributor
Honored ContributorSignal timing may change with implementing DDR2 interface and IP. The first question is, how you achieved phase alignment in the original design for LVDS receivers at the Cyclone III. Another, what' the nature of the transmission errors?
