Altera_Forum
Honored Contributor
10 years agoAdder IP block with different bus widths
I'm porting a design from a Xilinx device to a Cyclone5 and am trying to find a comparable signed arithmetic IP blocks using varying width inputs and outputs.
ALTERA_MULT_ADD works well for for my multipliers and I can specify the input output widths as needed, however I'm not seeing a comparable add/sub block. It looks like LPM_ADD_SUB only supports same data width inputs and outputs, i'm looking for something that could be configured with input widths of 28 and 29 and an output width of 30 bits. Is anyone aware of an Altera IP block that will support this?