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Altera_Forum
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10 years ago

ADC IP Core Issue

Hi, I'm trying to implement an ADC core with the core variant as ADC control core only in MAX10. I enabled the debug path for ADC1 as well as CH 0 of ADC1. In Qsys I made all the connections as...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Have you checked that you are feeding in a clock signal? And that you are not holding the system in reset.