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Are the registers for 'frame' and 'magnitude' operating in the exact same clock domain (ie, clocked from @(posedge clk) )?
Is the output port of ALTSQRT that 'magnitude' comes from registered on @(posedge clk) ?
A 122MHz clock rate is a period of 8.2ns. A 14ns setup error says that the clock period needs to be 22.2ns minimum, or about 45MHz Fmax.
I would try registering the output of ALTSQRT into 'magnitude' on @(posedge clk) just to see how that works.
You don't explicitly say the width of 'accum' but I am inferring it is 33 bits. I would think that device can do a 33b add in 8.2ns or less.
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All signals including frame, magnitude, ALTSQRT inputs, outputs operate in the same clock domain, 122.88 MHz.
The ALTSQRT IP output is the magnitude signal.
The magnitude signal is the input of this always statement:
always @ (posedge clk)
if (frame)
accum <= 33’h0;
else
accum <= accum + magnitude;
The magnitude width is 19 bits.
The accum width is 33 bits.
The frame signal is asserted every second clock cycle.
The data rate is 61.44 Msps.
The new sample comes from ALTSQRT IP every ~16.4 ns.
I don't register output of the ALTSQRT IP. I will try it.
Thanks,
Mike
Honored Contributor
