Accessing DDR-Ram from FPGA on DE1-SoC

Hi,

I’m trying to write data directly to the HPS DDR3-RAM on my eval board.

Problem is, I’m quite new to FPGAs in general and so after a bit of research I ended up with the following idea:

I thought of use this: https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html

Avalon MM Template to address the HPS (f2h_sdram0 Avalon-MM Write-Only 32)

I wrote a Verilog file containing a state machine to fill the required registers of the template according to its manual.

From what I see the master_crtl_done flag gets set, but I can’t see the written data.

To test my data transfer I tried to write some data to the ram which can be seen from the Linux system running on the SoC, using memtool I wanted to see if there is a change. But it seems this doesn’t work (no changes in memory)

Can someone tell me if this is a valid way to write to the memory or if my whole idea is wrong (as said I’m quite new to this only a few weeks in).

Or if I just messed something up.

Thanks in advance!

module mem_access (
  clk,
  reset_n,
  master_crtl_fixed_location,
  master_crtl_write_base,
  master_crtl_lenght,
  master_crtl_go,
  master_crtl_done,
  master_user_write_buffer,
  master_user_buffer_input_data,
  master_user_buffer_full,
  but0,
  led
);
  input    wire clk;
  input    wire reset_n;
  output    wire master_crtl_fixed_location;
  output    wire master_crtl_write_base;
  output    wire master_crtl_lenght;
  output    wire master_crtl_go;
  input    wire master_crtl_done;
  output    wire master_user_write_buffer;
  output    wire master_user_buffer_input_data;
  input    wire master_user_buffer_full;
  input    wire but0;
  output    wire  led;
  
  parameter    IDLE = 5'b00001, STATE1 = 5'b00010, STATE2 = 5'b00100, STATE3 = 5'b01000, STATE4 = 5'b10000;
  reg         state_but    = 1;
  reg     state            = IDLE;
  
  reg dataToWrite;
  reg writeBuffer;
  reg startWriting;
  reg  led_int         = 4'b0000;
  reg startAddress        = 'h10000000;
  always @ (posedge clk) begin
    case(state)
       IDLE:     
            begin 
                if (but0 == 1 && but0 != state_but) state <= STATE1;
                //led_int = 4b'0000;
                if (led == 1) led_int <= 0;
            end        
        STATE1:    
            begin 
                dataToWrite <= 13;
                state <= STATE2;
                led_int <= 1;
            end
        STATE2:    
            begin 
                if (master_user_buffer_full != 1) writeBuffer <= 1;
                else writeBuffer <= 0;
                state <= STATE3;
                led_int <= 1;
            end
        STATE3:
            begin
                startWriting <= 1;
                //writeBuffer <= 0;
                state = STATE4;
                led_int <= 1;
            end
        STATE4:
            begin
                startWriting <= 0;
                if (master_crtl_done == 1) 
                    begin
                        state = IDLE;
                        startAddress <= startAddress + 1;
                    end
                led_int <= 1;
            end
     endcase
     
    state_but = but0;
  end
  
  assign master_crtl_fixed_location        = 0;
  assign master_crtl_write_base             = startAddress;
  assign master_crtl_lenght                = 4;
  assign master_user_buffer_input_data    = dataToWrite;
  assign master_user_write_buffer        = writeBuffer;
  assign master_crtl_go                     = startWriting;
  assign led                                    = led_int;
  
endmodule