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Altera_Forum
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7 years ago

Accessing DDR-Ram from FPGA on DE1-SoC

Hi, I’m trying to write data directly to the HPS DDR3-RAM on my eval board. Problem is, I’m quite new to FPGAs in general and so after a bit of research I ended up with the following idea: I t...
Altera_Forum's avatar
Altera_Forum
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7 years ago

You should put some signaltap probes around your Avalon master to see what it is doing and what it is writing, to what address.

Also on the software side, remember to invalidate the data cache before attempting to read the memory back, or the CPU will just read from its cache instead of the SDRAM.