Contributor
Regular ContributorHi Lambert,
The core clock network sharing will necessary the PLL reference clock sharing.
One of the interfaces will be a master and the other will be slaves.
The master and slaves are used the same reference clock and the output clocks signals are also same.
So you are right for your questions.
But I'm still working on to provide the answer for the question 4.
For the burstcount, it is limited to width of 1 - 11.
The minimum burst is 2^1 and the maximum burst is 2^11.
So for your design, you can create the burstcount of 2^7.
And by the way, the maximum burst length for Arria 10 external memory interface IP is 127 which is equivalence to 2^11.
You can refer to the Avalon Interface Specification document in the link below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
Thanks,
Adzim
ContributorHi Adzim,
I don't do the thing that compares the phase of the emif_usr_clk from the ddr4 master and ddr4 slave, just because I got your answer. About the problem4, I use one async_fifo to store the ddr4 commands which generated through timinged to emif_usr_clk of ddr4 master for the ddr4 slave, but I still want to get one real reason about this problem just because the efficiency issues so that I must wait that the slowest one finishes the current burst operation before next burst operation(specially wr2rd or rd2wr switch operation).
Besides, for the avalon interface of the ddr4 controller, which is better for instancing one avalon source IP or use my own logic to emunite one avalon source IP? Now I chose later, but I feel it's not good though I satisfy the timing requirement for the avalon interface.
Brs,
Lambert
