Forum Discussion

lambert_yu's avatar
lambert_yu
Icon for Contributor rankContributor
4 years ago

About lvds serdes application

Hi all,

I face one problem, now I need use lvds serdes to do one transmitter, I need to get one dedicated clk for IO_PLL (I need external pll mode) from another bank due to the pin assignment for data lane and clock lane assignment at current bank. So I run the I/O assignment analysis in the pin planner, there is always one LVDS_CLK_TREE error, which means that this solution can not complete.

About above the problem, I found that the lvds serdes ip can droven by the IO_PLL from its adjacent bank, so I do not know what happens, could someone give me some advice?

FPGA : 10ax115n2f45e1sg

quartus pro : 16.0

Brs,

Lambert

2 Replies

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hello Lambert,

    Can you share me what error did you receive?

    Thanks

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      4 years ago

      We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.