Contributor
Regular ContributorHi,
As I understand it, you have some inquiries related to the XCVR dynamic reconfiguration. To ensure we are on the same page, just to check with you on the following:
1. What is the FPGA that you are using?
2. Which Quartus version are you using?
3. I understand that the RX parallel data seems to be having incorrect word boundary when you reconfigure to a specific data rate. To further narrow down the problem, just to check if you have had a chance to perform a Modelsim simulation with your design? This would be helpful to isolate any functional problem prior to hardware testing.
Please let me know if there is any concern. Thank you.
ContributorHi cheepin,
1. arria 10 , 10ax115n2f45e1sg
2. quartus 16.0
3. from the simulation result, there's no error.
Now, just through some delay between POR (default data rate stable) and next dynamic reconfig(same data rate), it can work.
But now I have another question, after dynamic reconfiguration of RX simplex, refclk is okay, cal_busy is de-asserted, ana_rst and dig_rst sequence is okay, CDR can not lock sometime and locktoref is not asserted. And I manually set ana_reset and dig_reset, CDR can not lock to refclk yet, I don't know what's wrong.
Brs,
Lambert
