Honored ContributorI using DMA and SDRAM IPcore in SOPCbuilder,transfer function is ok.but DMA's output per data need two clock cycle, efficiency is low,I hope DMA's output data with per clock,How to do?I using FPGA is EP2C8,SDRAM is HY57V16160,read and write data width is 16 bit.
Honored ContributorDid you enable burst transfer?
And what about using double clock frequency? But then take care about the refresh cycles automatically started from the SDRAM controller.Honored ContributorCan you describe the transfer a bit more? i.e. is it SDRAM --> peripheral, peripheral --> SDRAM, or SDRAM --> SDRAM? If it's the latter then you should only expect a write every 2 cycles (you can't read and write from SDRAM during the same cycle)
Honored Contributorit is SDRAM --> peripheral, DMA controller only read in SDRAM,how to up transfer speed?
Honored ContributorI have uncovered a situation where the DMA only transmits at half speed but I didn't expect your configuration to cause this. My fix for this issue is to insert a pipelined bridge into the data path (or multiple bridges) to increase the read latency to four cycles or greater. Since you are using SDRAM I don't think you are affected by this since the latency will be well over four cycles. If you like you can email me your system in either .ptf or .sopc format and I can take a look at what could be causing this. .ptf files were used up to version 7.0 of the tools and the switch occurred when 7.1 came out.
I also recommend capturing the DMA behavior in simulation and/or signaltap which may bring light to this issue. So that you are aware, the SDR SDRAM controller in SOPC Builder although capable of back to back reads, is prone to performance issues during bank switching or row switching. This could cause interruptions in DMA transfers as well (but I wouldn't expect a constant 2 cycle performance hit like you are claiming to see). Cheers, JCJB
