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Honored Contributor
Honored Contributorabout DMA transfers speed
I using DMA and SDRAM IPcore in SOPCbuilder,transfer function is ok.but DMA's output per data need two clock cycle, efficiency is low,I hope DMA's output data with per clock,How to do?I using FPGA is...
Altera_ForumHonored Contributor
Honored ContributorCan you describe the transfer a bit more? i.e. is it SDRAM --> peripheral, peripheral --> SDRAM, or SDRAM --> SDRAM? If it's the latter then you should only expect a write every 2 cycles (you can't read and write from SDRAM during the same cycle)
