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Altera_Forum
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18 years ago

about DMA transfers speed

I using DMA and SDRAM IPcore in SOPCbuilder,transfer function is ok.but DMA's output per data need two clock cycle, efficiency is low,I hope DMA's output data with per clock,How to do?I using FPGA is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Can you describe the transfer a bit more? i.e. is it SDRAM --> peripheral, peripheral --> SDRAM, or SDRAM --> SDRAM? If it's the latter then you should only expect a write every 2 cycles (you can't read and write from SDRAM during the same cycle)