Forum Discussion
Hi,
Upon checking internally, the <install_dir>/ip/altera/ altera_pcie/altera_pcie_a10_ed/ example_design/a10/sriov2_top_target_gen3x8_1pf_4vf.qsys is the example design and you do not need to regenerate the example design using the IP GUI. Regarding the simulation, you have to rename the qsys file to top.qsys and generate the testbench system following the steps in 2.3.
I tried to simulate the design with the name sriov2_top_target_gen3x8_1pf_4vf.qsys and top.qsys. The sriov2_top_target_gen3x8_1pf_4vf.qsys gives error message: Error loading design and the top.qsys simulation is successful.
Could you try to rename the qsys to top.qsys before testbench generation?
Thanks
Best regards,
KhaiY
- mark_lee4 years ago
Occasional Contributor
Hi KhaiChein
I had rename the Qsys file to top.qsys ,and sucess Compiling and Simulating the Design for SR-IOV in ModelSim with the message " Simulation stopped due to successful completion! Simulation passed"
Is the "sriov2_top_target_gen3x8_1pf_4vf.qsys" only for Simulating by ModelSim ?
What I want is an sr-iov example designs for A10 ,which can be run on my board include drivers for the host PC (linux in my case).
In intel web there have sr-iov example designs for S10, but I can,t find the download link like this page: