New Contributor
Frequent ContributorHi Sir,
For the timing diagram and AVMM specification, you can refer to Avalon Interface specifications. For Avalon Memory-Mapped Interface, you can refer to this chapter.
You can see on this chapter, it explain the details of each avalon mm signals and there is timing diagram for clearer understanding.
At the same time, you can generate the example design of the DDR4 IP and run simulation. On the simulation, you can check the traffic pattern of the avalon mm interface.
To run simulation of the example design, refer to this chapter of the external memory hadbook:
Hope this helps.
New ContributorHello,
Thanks for the response. I have seen the links you mentioned.
My question might be more naive; let me ask again with some details: I am running the core at quarter speed. On the AVMM side I see 128bit data interface. My interface to external memory is 16bits. Does this mean that for efficient use of the memory interface, I need to always write/read 128-bit wide data? I am trying to understand what happens if I only use the lower 32-bits? How do I manage the byte_enable and burst_count? I think having some example or timing diagrams on the use of the AVMM interface specifically for EMIF would be very helpful.
If anyone can explain me this (even in English); I will really appreciate it. Warm Regards!
