Contributor
Regular ContributorHi,
As I understand it, you have some inquiries related to the MII interface of the CPRI IP. For your information, this interface is fully compliant to the IEEE 802.3 100BASE-X 100Mbps MII specification. The CPRI IP include the Ethernet PCS block. You would need to code or add the other layers ie MAC to interface with the MII interface.
As I understand it from the user guide, the IP generated example design have simulation which demonstrate some transaction to MII interface. You may refer to the "Understanding the Testbench" section in the CPRI user guide for further details.
Regarding your inquiry on the reference Linux driver, sorry as I do not have any insight on this and could not comment on it. Sorry for the inconvenience.
Please let me know if there is any concern. Thank you.
ContributorThanks CheePin for reply,
So according to your suggestion, a general usage of CPRI Mii interface is " customer need to instantiate a 100M Ethernt MAC IP, and connect it to that cpri mii signal interface ". thus the Host driver would communicate with the FPGA MAC IP to treat it as a standard “ethernet device", correct ?
Then I may have raise a new question:
1) our FPGA card use PCIe link inside Host Machine, From host point of view, it's a PCIe EP, and it works as a CPRI FH Card for IQ transmit & Receiving.
2) If we enable CPRI MII i/f, and connect it to a FPGA internal MAC IP. In my opinion, we need expose it as a "standard" ethernet device point in Host Linux World (such as, “eth1” alike), thus we can operate it alike standard ETHERNET PORT.
MY Wonder : does it mean the single FPGA PCIE card should implement the multi-function Endpoint functionlity ( one is CPRI IQ DATA tx&rx function; and another is a *standard* ETEHRNET fucntion), so Host OS can load seperate drivers for them one by one ?
is it correct ? DOes ARRIA10 support "a multi-function Endpoint" usage case ? Thanks in advance
