Altera_ForumHonored Contributor15 years agoa problems about using posedge always @ (posedge clk or negedge alarm_in) begin if(cnt_s == set_s && cnt_m == set_m && cnt_h == set_h) alarm_outr <= 1'b1; else if(alarm_in == 1'b0) begin alarm_outr <= 1'b0; ...Show More
Altera_ForumHonored Contributor15 years agothanks i tried your way to design .... it can synthesized ... thanks again
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