a problems about using posedge

Referring to your original code snippet

always @ (posedge clk or negedge alarm_in)
begin
if(cnt_s == set_s && cnt_m == set_m && cnt_h == set_h) 
alarm_outr <= 1'b1;
else if(alarm_in == 1'b0) begin
alarm_outr <= 1'b0;
end

It does not involve dual clock edges as supected by nplttr, because alarm_in isn't a clock. The code uses the Verilog syntax for an asynchronous reset, but with a wrong order (and unpaired begin end). This way it should synthesisze correctly. If you think the order of the original code is essential, then you have a problem...

always @ (posedge clk or negedge alarm_in)
begin
if(alarm_in == 1'b0) 
  alarm_outr <= 1'b0;
else
  if(cnt_s == set_s && cnt_m == set_m && cnt_h == set_h) 
    alarm_outr <= 1'b1;
end

Generally, you should consider that an edge sensitive always block stands for a DFF, possibly with additional asynchronous inputs. It can be driven by only one clock. So one register can't appear in multiple always block as assignment target.