a problems about using posedge

if i have two signal to determine the outcome, i can't put the outcome variable into two always blocks.... so i have to put them into one always block

for :

always @ ( in1 or in2)

if (in1=1) a =b ;

else ....

i can't change them into

always @ (in1)

if (...) a=b ;

always @ (in2)

if(...) a =d

so there is always some time i have to put some clock in one block;

if i put them into one block,then i meet the problem like the previous one

do u have good way to design or handle this situation?

i try this way:

alarm = ((cnt_s == set_s) && (cnt_m == set_m) && (cnt_h == set_h))? 1'b1:alarm_in;

the same logic

however it still warning this:

Warning (10236): Verilog HDL Implicit Net warning at timeinterrupt.v(116): created implicit net for "alarm"

:confused::confused::confused: