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Altera_Forum
Honored Contributor
Honored Contributora problems about using posedge
always @ (posedge clk or negedge alarm_in) begin if(cnt_s == set_s && cnt_m == set_m && cnt_h == set_h) alarm_outr <= 1'b1; else if(alarm_in == 1'b0) begin alarm_outr <= 1'b0; ...
Altera_ForumHonored Contributor
Honored ContributorIt is not possible to synchronize on both positive and negative edge of a clock. Evene worse if you want to trigger on two clocks.
I suggest to synchronize everything on one clock. Then start with a check on the condition being zero for the remaining signal.
