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Altera_Forum
Honored Contributor
Honored Contributora problem in using the fifo
Recently, i designed a project, in the project i used fifo ip core. the fifo has wraddr and rdaddr port. As my understanding , if i read the fifo , these two address should decrease, if i write t...
Altera_ForumHonored Contributor
Honored Contributorthank you very much.
the write clock comes from the transceiver's rxclkout, the read clock comes from a vcxo from outside. now when the fifo is in wrong state , other logic will reset the fifo. but this can not totally solve the fifo's problem. The problem always appeared as the device just startup. When the device is working , the problem will not appear.
